The present invention relates to a technology for a semiconductor integrated circuit device and, more particularly, to a technology which is particularly effective for a semiconductor integrated circuit device with a special application such as an ASIC (Application Specific Integrated Circuit).
A gate array exemplifies a semiconductor integrated circuit device representing the ASIC.
The gate array is disclosed on pp. 72 to 73, 307 of Digest of Technical Papers, ISSCC (International Solid-State Circuits Conference), 1988, for example.
A semiconductor chip constructing the gate array is usually arranged with an internal circuit region. This internal circuit region is arranged with a plurality of basic cells.
The basic cell is a cell which is arranged with semiconductor integrated circuit elements such as transistors necessary for constituting one basic circuit (e.g., a gate circuit). The wiring connections between the basic circuits of the individual basic cells are changed to form a desired semiconductor integrated circuit in the internal circuit region.
This internal circuit region is arranged therearound with a peripheral circuit region. This peripheral circuit region is arranged with a plurality of input/output circuit (as will be shortly expressed as I/O) cells. The I/O cells are cells which are arranged with semiconductor integrated circuit elements such as transistors necessary for constituting an input/output circuit such as a standard input buffer circuit or a standard output buffer circuit. Each of the I/O cells is arranged with one corresponding bonding pad.
Over the I/O cells, on the other hand, there are arranged a plurality of peripheral power supply lines which are extended along the internal circuit region. The peripheral power supply lines are lines for feeding the power voltages to the input/output circuits of the peripheral circuit region and the semiconductor integrated circuits of the internal circuit region. The peripheral power supply lines are usually divided into two kinds: a peripheral power supply line for feeding a reference voltage V.sub.SS of about 0 V; and a peripheral power supply line for feeding a higher potential V.sub.DD of about 5 V.
The construction of tile I/O cells of the gate array is disclosed in EP (i.e., European Patent)-A-0349294, for example. On the other hand, the peripheral power supply lines are disclosed in U.S. Pat. No. 5,083,181, for example.